1. Field of the Invention
The present invention relates to a voltage level shift system and method, and more particularly, to a voltage level shift system and method between a core device and a peripheral device.
2. Description of the Related Art
Conventional voltage level shift circuits for use between a core power supply and an input/output ("I/O") portion in a microchip are known. Conventional voltage level shift circuits shift a voltage signal from a lower voltage level at the core power supply, e.g., 2.5 volts, to a higher voltage level necessary for the I/O portion of the microchip.
FIG. 1 illustrates a conventional voltage level shift circuit 10. The conventional voltage level shift circuit 10 includes an input signal line 12, a first inverter 15, a n-channel metal-oxide semiconductor field-effect transistor ("MOSFET") 20, a second inverter 25 a p-channel pull-up transistor 30, a low voltage supply rail 35, a high voltage supply rail 40, and an output signal line 42. The low voltage supply rail has a voltage of V.sub.DDL =2.5 volts and the high voltage supply rail 40 has a voltage V.sub.DDH =3.3 volts.
The input signal line 12 is coupled to the core power supply (not shown) and the first inverter 15. The first inverter 15 is coupled to the low voltage supply line 35 and the n-channel MOSFET 20. The n-channel MOSFET is coupled to the low voltage supply line 35, a drain of the p-channel pull-up transistor 30, and the second inverter 25. A source of the p-channel pull-up transistor 30 is coupled to the high voltage supply line 40 and a gate of the pull-up transistor 30 is coupled to the output signal line 42. The second inverter 25 is coupled to the high voltage supply line 40 and the output signal line 42.
When the conventional voltage level shift circuit 10 receives a voltage signal that transitions from a high voltage to a low voltage (e.g., 2.5 volts to 0 volts) from the core power supply, the input voltage signal is inverted to a logic high by the first inverter 15 to a voltage of 2.5 volts. The 2.5 volt signal is passed by the n-channel MOSFET 20 to the second inverter 25.
The n-channel MOSFET 20, however, reduces the voltage signal by a threshold voltage, V.sub.T =0.7 volts, so that the second inverter 25 receives only a (V.sub.DDL)-(V.sub.T)=1.2 volt signal (2.5 volts (V.sub.DDL)-0.7 volts (V.sub.T)). The second inverter 25 must wait for the p-channel pull-up transistor 30 to pull the voltage level up to VDDH=3.3. volts, and the triggering signal for the second inverter 25 will not be more than (V.sub.DDL)-(V.sub.T) volts. Therefore, the voltage signal transition from a logic high to a logic low in conventional voltage level shift circuits 10 will have more delays than a transition from a logic low to a logic high.
Thus, conventional voltage level circuits 10 are not suitable for low-input voltage applications because the voltage drop through the n-channel MOSFET 20 is too large to allow the second inverter 25 to invert the voltage signal to trigger transitions between low and high in a timely manner. That is, the time required to pull-up the voltage to an adequate level that allows the second inverter 25 to invert the signal adds delays to the operation of the circuit. These delays slow down overall circuit performance and result in decreased overall system performance. Moreover, conventional voltage level shift circuits 10 require greater system resources, for example, a greater power draw to accommodate for the need to raise voltage levels to a level that is necessary to properly perform functions such as properly transitioning between logic lows and highs in a timely manner.
Therefore, there is a need for a voltage level shift system and method that allows for signal transitions between two signal levels in a manner that increases overall system performance with less power consumption.